68000 Microprocessor Support
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- Full speed state analysis up to 16.666 MHz
- Disassembly shows acquired data in the processor's instruction set mnemonics.
- Symbolically identifies all processor bus cycles
- Acquired data can be linked directly to HLL source files for source level debug
- 500 ps timing resolution enables detailed analysis of setup and hold times, edge-to-edge relationships, control timing, etc.
- All data acquired by the logic analyzer is time stamped to enable accurate time correlation of code execution to other system busses or hardware activity.
Probing and Package Styles
- Probe adapter designed for a socketed 64-pin DIP package for 68000/010.
- Probe adapter designed for a socketed 68-pin PLCC package for 68EC000.
Minimum System Requirements
- TLA7xx mainframe and one TLA7L2 acquisition module, 68 channels, 100 MHz state, 32K deep (200 MHz state, up to 136 channels and up to 64M deep available)
- Or TLA602 instrument, 68 channels, 100 MHz state, 32K deep (200 MHz state, up to 136 channels and up to 1M deep available)
- add qty 6: P6417 -or- P6418 general purpose probes (REQUIRED)
- TLA application software version 1.0 or greater
- Instrument setup software including clocking and channel assignments
- Symbol table of all bus cycle names
- Disassembler for 68000, 68EC000 and 68010 processors
- Probe adapter for a socketed 164-pin DIP package or 68-pin PLCC package.
- User manual
|device description||product number|
|add qty 6: P6417 -or- P6418 general purpose probes (REQUIRED)||P6417/P6418|
Last Modified: 1996-12-13 04:00:00