DG2020A

Data Pattern Generator
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Features & Benefits

  • Data Rate to 200 Mb/s
  • Data Pattern Depth 64 K/channel Speeds Characterization
  • Multiple Output Channels Increases Flexibility
    • DG2020A: 12, 24, or 36
  • Precise Control of Output Parameters Include:
    • Variable Output Delay
    • Variable Output Level
    • Tri-state Output Control
  • Transition Times 2 ns at 5 Vp-p
  • Flexible Sequence Control with Jump, Event, and Nested Loops
  • Large Display for Easy-to-Use Data Editing
  • Import Pattern Data with DG-Link Software Utility
  • Integrate into ATE Systems through GPIB/RS-232-C Interface

Applications

  • Low Jitter for Clock Substitution
  • Characterize Device Timing
  • Simulate Missing Functions in System or Subsystem Evaluation
  • Create Complex Data Patterns with Sophisticated Sequence, Looping, Jump on Event, and Tri-state Output Control
  • Characterize and Verify ASIC, FPGA, and DACs
  • Test Printer Engines or LCD Display Drivers
  • Construct Logic Verification Systems Utilizing Tektronix Oscilloscopes or Logic Scopes
  • Use in Conjunction with TLA Logic Analyzer to Provide Digital Stimulus

 

The DG2020A pattern generator provides digital designers with the high-performance tools needed to evaluate digital semiconductors and logic circuits. Whatever you call your design process - characterization, debug, validation, or verification - as a digital designer you must have a state-of-the-art digital pattern generation as you push the edge of the technology envelope and race to market.

The DG2020A is an appropriate instrument for a wide variety of digital design applications. The table illustrates the principal specifications for the DG2020A.

DG2020A

Characteristic

Description

Data Rate

200 Mb/s

Pattern Depth

64 K/CH.

Rise/Fall Time

(20% to 80%)

2 ns at 5 Vp-p

No. of channels

12, 24, or 36

Features

Bus-wide testing

Critical Timing

The DG2020A is the ideal solution for applications where you must characterize device or circuit timing and amplitude margins. The DG2020A graphical user interface allows you to quickly create complex data patterns with a few keystrokes on the front panel. Use the advanced sequence editing capability to insert infrequent faults or glitches in your data patterns to verify device or circuit recovery. The DG2020A is an invaluable tool, allowing you to simulate missing system functionality while meeting critical market windows.

Excellent Signal Flexibility

The DG2020A outputs data at rates up to 200 Mb/s with 64 K data word length on up to 36 channels (12 standard) in 12-channel increments with 100 ps timing control. The P3420 variable output pod provides 500 mVp-p to 9 Vp-p (-3 V to 7 V) in 100 mV steps. SMB connectors are used for each channel. The P3420 is capable of sourcing >30 mA current per channel - enough for your most demanding applications.

Pattern Editing
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Figure 3. Examples of data entry displays. Data is entered easily as hex data or diagrammatically.

The DG2020A is designed for serious digital designers who create their own digital patterns or rely on a logic simulator to supply digital vectors. A large graphical display simplifies data entry and editing functions, allowing the user to easily view and shape large segments of the data pattern (Figure 3). A wide variety of commonly used data patterns are built into the data editor to further simplify data creation. Built-in data functions include counters, shift registers, serial data converters, and clocks.

Easy-to-use menu-driven editing functions are provided to define data bit, cursor location, and data width. Data can be manipulated at the bit, byte, or word level. Various functions such as data cut/copy/paste, invert, magnify, insert, and delete are supported, as are data shift, add, and rotate. Advanced functions are used to create clock patterns and PRBS data. A variety of data presentations are available to clearly illustrate the data pattern including table, timing, binary, and numeric.

Pattern Sequencing
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Figure 4. Flow chart illustrates sequence control flow.

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Figure 5. Examples of editing menus showing automatic data pattern generation and editing tools.

The DG2020A includes advanced data flow sequencing to provide the designer with a flexible digital stimulus source. Pattern sequencing is a capability that can extend the deep DG2000 Series pattern memory almost to infinity. Sequencing allows segments of pattern memory to be looped or repeated until some internal or external event occurs when pattern execution then continues. Each line in the sequence list can be controlled by an external event that can cause a jump to a different block of data. The DG2020A can have up to 2048 jumps at full clock rates.

 

Three types of sequences are offered:

  • Simple Sequence - For repeat, single, or step operation modes
  • Enhanced Sequence - Supports more interactive and dedicated sequence control
  • Subsequence - Supports defined subsequences that manage multiple blocks as a single block. Uses only one sequence entry in the sequence definition table
Import Data
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Figure 6. DG-Link software utility imports ASCII data vectors.

Tektronix' DG-Link software accessory imports data from Tektronix TDS oscilloscopes, TLS logic scopes, or TLA logic analyzers for use as data pattern sources by the DG2000 Series. Logic simulators that output Comma Separated Value (CSV) format can also be used as a source file for DG-Link and downloaded into the DG2000 Series.

Characteristics

Output Data

Data Rate - 0.1 b/s to 200 Mb/s.

Sampling Rate - 0.1 Hz to 200 MHz.

Resolution - 4 digits.

Clock Output Period Jitter - <50 psp-p at 200 MHz, typical.

CH0 Period Jitter (clock pattern) - <35 psp-p at 200 MHz, typical.

Accuracy - PLL On, ±0.005%; PLL Off, ±3%.

Pattern Depth - 64 to 64 Kbits (1 increment).

Data Width -

Standard: 12 bits.

Optional: 24 or 36 bits.

 

Sequencer

Maximum Number of Blocks - 256.

Maximum Number of Sequence Steps - 2048.

Block Repeats Per Line - 1 to 65536 or infinite.

Auxiliary Inputs

Clock - Rear-panel SMB connector.

Frequency: DC to 200 MHz.

Impedance: 50 Ω, terminated to +0.5 V.

Delay to Clock Out: 36 ns (typical).

 

Trigger - Front-panel BNC connector.

Level: -5.0 V to +5.0 V.

Resolution: 0.1 V.

Threshold Accuracy: ±(5% of setting) ±0.1 V.

Minimum Pulse Width: ≥10 ns.

Sensitivity: >0.5 Vp-p.

Impedance: 1 kΩ or 50 Ω.

Maximum Input: ±10 V into 1 kΩ, ±5 V into 50 Ω.

Polarity: Positive or negative.

Hold Off: 500 ns minimum.

 

Auxiliary Outputs

SYNC - Front-panel BNC connector.

Level:

VOH, 2.5 V into 50 Ω.

VOL, 0 V into 50 Ω.

Pulse Width: 6 clocks.

Impedance: 50 Ω.

 

EVENT - Front-panel BNC connector.

Level: Positive TTL pulse, 50 Ω.

Output Term:

DG2020A: 8 clocks.

Delay Time: 22 clocks before data output change.

Impedance: 50 Ω.

 

CLOCK -

Rear-panel SMB connector.

Level: 1 V (typical) into 50 Ω.

Delay From Trigger Input:

PLL On:

>6.25 MHz: 15 to 40 ns.

<6.25 MHz: 25 to 60 ns.

PLL Off:

>6.25 MHz: 15 to 45 ns.

<6.25 MHz: 25 to 60 ns.

External: 7 ns + 1 clock to 20 ns + 0.5 clock.

 

Programmable Interface -

GPIB: ANSI/IEEE 488.2-1987.

RS-232-C: 19.2 Kb/s, D-sub 9-Pin connector.

 

P3420 Variable Data Output Pod Characteristics
Data Output

Channels - 12.

Connector - SMB.

VOH - -2.0 V to +7.0 V into 1 MΩ.

VOL - -3.0 V to +6.0 V into 1 MΩ.

Resolution - 0.1 V.

Maximum Swing - 9.0 Vp-p.

Minimum Swing - 0.5 Vp-p.

Output Current -

Total Output Current: <500 mA.

Sink: < -30 mA/CH.

Source: > +30 mA/CH.

 

Rise/Fall Time - <2 ns into 1 MΩ, 10 pF, 5 Vp-p swing (20% to 80%).

Internal Clock Out to Data Delay - 20 ns.

External Clock Input to Data Output Delay - 20 to 40 ns.

Trigger Input to Data Output Delay -

Internal Clock:

>6.25 MHz: 30 to 60 ns.

<6.25 MHz: 40 to 70 ns.

External Clock: 20 ns + 0.5 clock to 40 ns + 1.5 clock.

 

Delayed Channels

Delay Channel - CH 8, CH 9, CH 10, CH 11.

Delay Time - 0 to 20 ns.

Delay Resolution - 0.1 ns.

Channel Skew -

CH 0 and other channels, same pod: <3 ns.

CH 0 and CH 0, two pods of same type: <2 ns.

 

Event Input

Threshold Level - -5.0 V to +5.0 V.

Resolution - 0.1 V.

Delay to Data Output - ≤45 ns + 50 clock.

Setup Time to Next Block - 47 to 54 clocks.

Inhibit Input

Threshold Level - -5.0 V to +5.0 V, 1 kΩ.

Resolution - 0.1 V.

Delay to Data Output - 16 ns.

Internal Inhibit Delay - -2 ns.

Physical Characteristics

Dimensions

mm

in.

Height*1

51

2

Width

255

10

Depth

161

6.3

Weight

kg

lb.

Net

1

2.2

*1 Including feet.

General Characteristics
Environmental

Temperature -

Operating: +10 °C to +40 °C.

Nonoperating: -20 °C to +60 °C.

 

Humidity -

Operating: 20% to 80% (no condensation).

Nonoperating: 5% to 90% (no condensation).

 

Altitude -

Operating: Up to 4.5 km (15,000 ft.).

Nonoperating: Up to 15 km (50,000 ft.).

 

Vibration - Operating: 0.33 mm p-p, 10 to 55 Hz, 15 minutes.

Shock - Nonoperating: 294 m/s2 (30 g), half-sine, 11 ms duration.

Certification and Compliance

EC Declaration of Conformity - Meets intent of Directive 89/336/EEC for electromagnetic compatibility.

Safety - UL1244, CSA231, EN61010-1, IEC61010-1.

Power

AC Line Power -

Voltage Ranges: 90 to 250 VAC.

Nominal Voltage: 100 V, 115 V, 200 V, 230 V, 240 V.

Line Frequency:

90 to 250 VAC: 48 to 63 Hz.

90 to 127 VAC: 48 to 440 Hz.

 

Power Consumption - 300 W maximum.

Maximum Current - 4 A.

Physical Characteristics

DG2000 Series Mainframe

Dimensions

mm

in.

Height*1

164

6.4

Width*2

362

14.3

Depth*3

491

8.25

Weight

kg

lb.

Net

9.7

21.4

*1 Including feet.

*2 Including handle.

*3 Including front cover. 576 mm (22.2 in.) with handle extended.

Characteristics shown are typical. Please refer to individual product user manuals for complete specifications.

Last Modified: 2011-10-18 05:00:00
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