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Tektronix and Cadence team up to enable 200Gb/sec data transfer speeds using DDR4 & LPDDR4 PHY IP

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High speed memory design is challenging. With faster read/write speeds and difficulty accessing components, key to a good DDR4 PHY is careful design across the SoC, package, board, and system challenges. To do it right, it helps to look to Tektronix and partners like Nexus Technologies, SK Hynix, TSMC and Cadence for IP, Simulation and Validation Test.

Read more about DDR testing and IP PHY development tools on this Cadence Design Blog.

Next-Generation DDR4 and LPDDR4 IP in TSMC 16FF+ Enable 200Gb+ Data Transfers for Mobile, Cloud, and IoT Platforms

Blogueurs

Electrochemistry Experts

Articles de blog : 7
Tektronix Experts

Articles de blog : 261
David Pereles

Articles de blog : 18
Joseph Gorley

Articles de blog : 3
Service Experts

Articles de blog : 11
Brian Hensley

Articles de blog : 2
Christopher Loberg

Articles de blog : 5
Alan Wolke

Articles de blog : 21
Andrea Vinci

Articles de blog : 1